AtomMiner Hardware Architechture
As of now, we use BeMicro Max10 FPGA Kit as a hashing module and USB-Serial breakout board from FTDI as a USB-Serial bridge between AtomMiner and host PC. Typical hardware data workflow is shown on the following diagram:
UART – Serial Communication Interface between host PC and hardware
MAXclocking – internal clocking module that provide on-the-fly frequency reconfiguration
system_control – Internal control module that can start/stop hashing and responsible for sending correct data back to UART block
system_ram – Internal on-chip memory to store source data block(s) and various internal constants and data
m1_sm and m2_sm<span”> – state machines necessary for SHA256 hash computation.
hash_cmplt and ticket2moon signals should initiate system_control<span”> to send hash response back to the host system.
Clock frequency clk_h can and will be changed every time set_clk command is executed by the host. You can read more about set_clk command in the AtomMiner – Hardware Communication Layer article.
This project has been done using Quartus Prime Lite 15.01 from Altera using Verilog programming language and was later tested on Quartus Prime Lite 17.0
The UART has been implemented using source code from the following resource http://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html and wanted to say that we really appreciate their time and efforts! Keep it up, guys!
You can download all the sources for this project at our GitHub page!
